1. Field of the Invention
The present invention relates to a memory device; and more particularly, to a memory device having a programmable device width, a method of programming the device width, and a method of setting a device width for a memory device.
2. Description of Related Art
In today's electronic manufacturing environment, many unique parts are required for both suppliers and consumers of electronic components. This is particularly true among memory components which comprise a large percentage of the overall system/device cost. With memory devices, the major part differentiators include access time, reliability grade, function, and device width.
For example, with respect to device width, a 16 Mb dynamic random access memory DRAM may come configured as either a 4 Mb.times.4, 2 Mb.times.8, 1 Mb.times.16, 512 Kb.times.32, etc. With a 4 Mb.times.4 configuration, the 16 Mb memory device is divided into four memory blocks of 4 Mb each, and has one input/output I/O corresponding to each memory block. Accordingly, when listing memory devices, a different part number is required for each memory device having a different device width.
Manufacturers of such memory devices produce a die which can operate as a .times.1, .times.4, .times.8, etc., device. Some manufacturers then set the device width of the die during the final metalization stages of the die's manufacture. Other manufacturers use different die packages to set the device width through wire bonding as described in detail below.
FIG. 1 illustrates a well known synchronous dynamic random access memory SDRAM with the device width set according to the well known wire bond option technique. As shown in FIG. 1, the SDRAM includes a clock generator 2 which outputs clock signals to various components of the SDRAM to synchronize the operation thereof. A command decoder 4 of the SDRAM receives a chip select CS, row enable RAS, column enable CAS and write command W inputs. As shown in FIG. 1, the command decoder 4 recognizes, for example, a write command when CS, CAS, and W are asserted, i.e., logic low, at the same time. The command decoder 4 outputs the command to the control logic 6 which controls the operation of the other components of the SDRAM based on the received command.
Besides the commands of CS, RAS, CAS and W, the command decoder 4 can also recognize other commands based on a combination of CS, RAS, CAS and W. For instance, the command decoder 4 decodes the simultaneous receipt of CS, RAS, CAS and W as a mode register set command.
When a mode register set command is received, the control logic 6 causes a mode register 8 to latch the address data on address inputs A0-A10 and BA0-BA1. The data on address inputs A0-A10, generally, represent either a row or column address and the data on address inputs BA0-BA1, generally, represent a bank address. The bank addresses inputs BA0-BA1 specify one of the memory banks A-D discussed in detail below. During the mode register set operation, however, the data on address inputs A0-A10 and BA0-BA1 do not represent addresses. Hereinafter, the address inputs and the data thereon will generically be referred to as address inputs.
FIG. 2 illustrates a table showing the current Joint Electron Device Engineering Council (JEDEC) standard 21-C version 6 encodation definition for each address input during the mode register set operation. As shown in FIG. 2, address inputs A0-A2 set the burst length, address input A3 sets the addressing mode, address inputs A4-A6 set the CAS latency, address input A7 enables a test mode, address inputs A8, A10, and BA0-BA1 are reserved for future use, and address input A9 sets the write mode. The control logic 6 then controls the components of the memory device according to these settings. Accordingly, like CS, RAS, CAS, and W, the data supplied on the address inputs during the mode register set operation are also command data.
Returning to FIG. 1, the SDRAM includes a row address buffer and refresh counter 10 and a column address buffer and burst counter 12 connected to the address inputs. The row address buffer portion latches the address inputs at RAS time, RAS enabled, and provides the address data to the appropriate row decoder 14. The refresh counter portion refreshes the chip. The column address buffer portion latches the address inputs at CAS time, CAS enabled, and provides the address data to the appropriate column decoder 18. The burst counter portion controls the reading/writing of more than one column based on the pre-set burst length.
The memory 22 of the SDRAM is divided into four memory banks A-D. In this manner, the memory banks A-D can be independently and simultaneously selected. Each memory bank A-D has associated therewith a row decoder 14, a sense amplifier 16 and a column decoder 18. Based on the address latched by the row address buffer and refresh counter 10, a row decoder 14 enables a row of bits. An associated sense amplifier 16 latches the columns of this row via sense amplification, and the associated column decoder 18 outputs one or more bits depending on the device width and burst length.
The SDRAM includes configuration logic 28 for setting the device width. The configuration logic 28 includes a plurality of program pads. When the SDRAM die is packaged, the packaging internally wire bonds the programs pads to either an input voltage VDD pin or a ground pin. Based on these connections, which set the logic state for each program pad, the configuration logic 28 configures the data control circuit 20, a latch circuit 24 and an input/output buffer 26 to obtain the device width associated with the logic states of the program pads. Specifically, the configuration logic 28 controls the switches and multiplexers in a data control circuit 20 such that the number of input/output drivers corresponds to the device width. For example, if the configuration logic 28 configures the data control circuit 20 to a .times.8 device width, the data control logic 20 will have eight input/output drivers. Likewise, the packaging will include eight I/O pins DQ0-DQ7. Accordingly, the configuration logic 28 configures the latch circuit 24 and the input/output buffer 26 to latch and buffer data between the eight I/O pins DQ0-DQ7 and the corresponding eight input/output drivers of the data control circuit 20.
The data control circuit 20 is connected to each column decoder 18, and is connected to data input/output pin(s) DQ(s) via the latch circuit 24 and the input/output buffer 26. During a read operation, the column decoders 18 output data to the data control circuit 20 based on the enabled row, the enable column, and the burst length. The data control circuit 20 then routes the data to the number of input/output drivers set based on the device width. The data from the input/output drivers is latched by the latch circuit 24, buffered by the input/output buffer 26 and output on the data input/output pin(s) DQ(s). As alluded to above, the number of input/output pin(s) DQ(s) corresponds to the device width. For instance if the device width is .times.1, then configuration logic 28 will have configured the data control circuit 20 to have a single input/output driver and the packaged SDRAM will have a single input/output pin DQ. Or, if the device width is .times.4, then the configuration logic 28 will have configured the data control circuit 20 to have four input/output drivers and the packaged SDRAM will have four input/output pins DQ0-DQ3.
During a write operation, the SDRAM receives data over the input/output pin(s) DQ(s). This data is buffered by the input/output buffer 26, latched by the latch circuit 24, and received by the data control circuit 20. The data control circuit 20 sends the data to the appropriate column decoders 18 for storage in the memory banks A-D according to the enabled row and column.
The SDRAM also includes an input DQM to the latch circuit for every 8 bits of input/output. For instance a .times.16 SDRAM will have two inputs DQM0 and DQM1. When enabled, the input DQM prevents reading or writing the remainder of a burst. In this manner, the burst length can be controlled.
As the discussion above indicates, the device width of a memory device is set during the final metalization of the memory die or by internal connections made during packaging of the die. While these two techniques of setting device width have been discussed above in detail with respect to SDRAMs, these techniques are also used to set the device width of DRAMs, read only memories ROMs, programmable read only memories PROMs, erasable programmable read only memories EPROMs, electrically erasable read only memories EEPROMs, etc.
At least one manufacturer, however, has pinned out the program pads by adding additional pins to the memory device package. The resulting device, however, did not meet JEDEC standards, and therefore, little or no demand exists for such products. Accordingly, manufacturers producing memory devices for the commercial market utilize either the final metalization technique or the bonding option technique to set device width.
While using these techniques provides the manufacturer with the flexibility to choose the device width, consumers must wade through the manufacturer's long lists of part numbers to find the particular memory device having the device width desired. For consumers wanting to purchase relatively unpopular types of memory devices, this only begins the arduous journey of obtaining a memory device of a desired device width. Typically, manufacturers will allocate more production runs to those memory devices having device widths which are in greater demand. Consequently, a consumer seeking a less popular memory device often finds theses devices out-of-stock, and must wait for the manufacturer to make a production run of that memory device.